In keeping pace with recent developments in semiconductor memory devices, techniques can be used to manufacture from a common semiconductor substrate a plurality of product types whose word structure, for the same memory contents, or control function differ.
As one example, FIGS. 9A and 9B show the external pin, or lead, arrangement of a 256K bit static random access memory ("SRAM"). Pins, or leads, extend out of the memory package for installation in a socket. There are 28 pins; fifteen address pins (A0-A14), eight input/output pins (I/01-I/08), VDD, VSS, and three control pins. The control pins in FIG. 9A are write control pin XWE, output control pin XOE, and chip select control pin XCS. All negative-logic signals in the figures and description begin with the letter X. Thus, all control pins in FIG. 9A are negative logic.
FIG. 9B shows an arrangement where a positive-logic chip select control pin, pin CS2, is used in place of pin XOE of FIG. 9A. Pin XCS1 continues to be the negative logic chip select control pin. In other words, pin 22 is changed from XOE to CS2. Users of the semiconductor memory devices can separate the use of the above two types from system structures. Particularly a memory having pins XCS1 and CS2 can be used in battery backup applications.
FIGS. 7A and 7B, as well as FIGS. 1, 3 and 5, depict circuit components on a chip in an IC package. Each element identified as a "Pad" is a bonding pad on a chip and can be connected to a selected pin by a bonding wire (not shown).
FIGS. 7A and 7B are circuit diagrams showing input circuits for the control signal in conventional semiconductor memory devices. FIG. 7A shows the input circuits for the XCS and XOE type control signals. FIG. 7B shows the input circuits for the XCS1 and CS2 type control signals.
In FIG. 7A, pad 20 is a bonding pad connected to a pin XCS for receiving and transferring an extend chip select signal which comes from outside the device. Pad 22 is a bonding pad connected to a pin XOE for receiving and transferring an output control signal which comes from outside the device. Although NOR gate 200 is an input stage for a positive logic chip select signal, in this memory type CS2 is not used. One input of NOR gate 200 is fixed to VDD and internal signal XCS2a is fixed or normally low. In the illustrated circuit, the other input of gate 200 is connected to VSS (ground) via a resistor 203. NOR gate 100 is an input stage for receiving the external chip select signal. One input of gate 100 is connected to pad 20 and the other input is connected to receive the above-mentioned signal XCS2a. Internal control signal XCS1b is output through inverter 101. Because XCS2a is normally low, XCS1b is synchronized with the external chip select signal. NOR gate 300 is an input stage which receives the output control signal. One input of gate 300 is connected to Pad 22 and the other input is connected to receive the above-mentioned signal XCS1b. Internal control signal XOEa is output through inverter 301. When the external chip select signal is low, in other words only during chip select, NOR gate 300 operates as XOE. When the XCS signal is high, that is to say during chip non-select, the operation of NOR gate 300 is inhibited and internal signal XOEa is fixed at the high level. This is to stop the data output operation from the memory device when in the non-select state, and at the same time prevents unnecessary current consumption at NOR gate 300 due to change in potential of the output control signal. Similarly, by taking the logic of an external address signal and XCS1b at the input stage of the address input circuit, low current consumption during non-select times can be realized. The operating waveforms of the conventional semiconductor memory device of FIG. 7A are shown in FIG. 8A. Internal signals XCS1b, CS2b, and XOEa are used as the basic signals to form the internal control signals of the memory device.
The conventional semiconductor memory device shown in FIG. 7B is exactly the same as the structure shown in FIG. 7A, except for: positive-logic chip select control signal at pin CS2 being supplied to Pad 22; one input of NOR gate 200 being connected to Pad 22; and one input of NOR gate 300 being connected to VSS by a resistor. With this construction, internal signal XCS2a becomes the inverse signal, or complement, of positive-logic chip select control signal at CS2. Internal signal XCS1b is synchronized with XCS1 when the CS2 signal is high and is fixed at the high level when the CS2 signal is low. Also, when the CS2 signal is high and the XCS1 signal is low, in other words when in the chip select state, internal signal XOEa goes low. When the CS2 signal is low or XCS1 is high, in other words when in the chip non-select state, internal signal XOEa goes high. The operating waveforms of the conventional semiconductor memory device of FIG. 7B are shown in FIG. 8B. Just as in FIG. 7A, internal signals XCS1b, CS2b, and XOEa are used as basic signals for forming internal control signals for the device.
When changing the product type of a conventional semiconductor memory device where the same semiconductor substrate is arranged with the necessary input circuit elements for a plurality of product types, a portion of the photomask for wiring, for example, metal masks (masks for metal wiring), are prepared for the memory types of FIG. 7A or FIG. 7B. The changes for these product types are then made at the time of wiring during the semiconductor manufacturing process. At the end of the manufacturing process, recognition of the product type is done by examining through a microscope the code or product number that is characteristic to the product type. These codes or numbers have been arranged within the semiconductor device using the previously discussed metal masking.
Due to the above construction of conventional semiconductor devices, the following problems exist.
Because product type changeovers are made by altering a portion of the photomask, a large number of photomasks becomes necessary in the development of the product types, so that there is a cost increase due to mask construction, as well as complications that arise in controlling these masks. Also, because changes in product type cannot be made after the wiring process, production control to determine the product type becomes a necessary process during the manufacturing processing and production levels cannot be regulated after manufacturing.
The purpose of the instant invention is to provide a semiconductor memory device that solves the above problems, whose manufacturing cost does not increase, and whose product types are able to be sorted out after the semiconductor manufacturing process.